Integrated circuit having a via and a capacitor
作者： David E. Kotecki , Jeffrey P. Gambino , Mark A. Jaso
DOI:
关键词:
摘要: An integrated circuit including a capacitor and method of manufacturing the simultaneously while forming dual damascene via. A first interconnect layer is formed upon interlevel dielectric. Openings corresponding to vias capacitors extend through second dielectric layer. conductor deposited in via openings. insulator openings on trench then etched into upper portion removing from trenches chemical-mechanical polishing (CMP) used pattern conductor. third deposited, are extending conductors, conductors patterned.
lens.org 参考文章(20)
George Kerr, Yves Meheust, Method of manufacturing an integrated capacitor and device obtained by this method ,(1983)
Naoto Matsuo, Semiconductor memory device with a capacitor having a protection layer ,(1994)
Zachary J. Lemnios, David G. McIntyre, Dennis A. Williams, Chung-Lim Lau, Three metal personalization of application specific monolithic microwave integrated circuit ,(1990)
Jerome F. Lapham, Mark A. Smrtic, George M. Molnar, Integrated circuit metal-oxide-metal capacitor and method of making same ,(1993)
Lap Chan, Jiazhen Zheng, Method of making a dual damascene antifuse structure ,(1996)
Thekkemadathil V. Rajeevakumar, High capacity dram trench capacitor and methods of fabricating same ,(1990)
William P. Ingram, Monta R. Holzworth, Pankaj Dixit, Richard Klein, Improved method of fabricating antifuses in an integrated circuit device and resulting structure ,(1991)
J.H. Ha, S.W. Kim, Y.S. Seol, H.K. Park, S.H. Choi, Reduction of loading effect by tungsten etchback in a magnetically enhanced reactive ion etcher IEEE Transactions on Semiconductor Manufacturing. ,vol. 9, pp. 289- 291 ,(1996) , 10.1109/66.492826
Hiroshi Yuzurihara, Yoshio Nakamura, Yukihiko Sakashita, Shunsuke Inoue, Shin Kikuchi, Method of manufacturing a semiconductor memory device containing a capacitor ,(1991)