作者: Chi-Hung Lin , M. Ismail
DOI: 10.1109/ICECS.1999.814501
关键词:
摘要: In this paper, synthesis and analysis of high-order cascaded continuous-time /spl Sigma//spl Delta/ modulator have been explored. A simple mixed-mode methodology is used to synthesize the cascade modulator. Mixed-mode simulation performed by MATLAB. 3rd-order 2-1 case demonstrated, also nonlinearities high order are analyzed, such as clock jitter loop delay.