Technique of forming over an irregular surface a polysilicon layer with a smooth surface

摘要: Techniques of forming a flash EEPROM cell array with the size individual cells being reduced, thereby increasing number which may be formed on semiconductor substrate given size. Use dielectric spacers in several steps process controls areas etched or implanted ions to something smaller than can obtained by highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types memory are included. Example employ three polysilicon layers, having separate floating, control erase gates. A technique gates greater uniformity conductivity level includes depositing undoped then using ion implantation introduce dopant. Field oxide is at an early stage CVD deposition dry etching. The adjacent peripheral components coordinated manner single integrated circuit chip.