Architecture to Improve Cell Size for Compact Array of Split Gate Flash Cell with Buried Common Source Structure

摘要: Some embodiments of the present disclosure relates to an architecture create split gate flash memory cell that has lower common source (CS) resistance and a reduced size by utilizing buried conductive structure. A two-step etch process is carried out recessed path between two cells. single ion implantation form also forms beneath STI region connects cells provide potential coupling during programming erasing thus electrically connect sources along direction CS line. The contains no OD line cells, eliminating effects rounding resistance, resulting in space array. Hence, this particular reduces several array suppresses area over head.