Evaluation of the Iddq Signature in devices with Gauss-distributed background current

作者: Jan Schat

DOI: 10.1109/DDECS.2008.4538793

关键词:

摘要: In the last decade, single-threshold IDDQ approach made way for more elaborated techniques like Delta-IDDQ and adaptive IDDQ. Due to increasing background currents, however, also these methods are beginning have problems distinguish between good bad devices. A evaluation algorithm takes all known information about 'good' 'bad' parts into account, i.e. it 'knows' how signatures of look like. Unfortunately, not only do differ significantly, but even more. Moreover, since faults often than non-fatal (not impairing functionality), is frequently hard say if a device really or bad'. There two kinds information, which without referring certain process IC type: one model fault, other statistical distribution background-IDDQ. Using this an estimator with higher discrimination capability traditional Delta-IDDQ-approach created. Measurement results form several lots 180 nm chip presented..

参考文章(18)
J.C.M. Li, E.J. McCluskey, IDDQ data analysis using current signature Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232). pp. 37- 42 ,(1998) , 10.1109/IDDQ.1998.730730
A. Ferre, J. Figueras, On estimating bounds of the quiescent current for I/sub DDQ/ testing vlsi test symposium. pp. 106- 111 ,(1996) , 10.1109/VTEST.1996.510843
A.E. Gattiker, W. Maly, Current signatures: application [to CMOS] international test conference. pp. 1168- 1177 ,(1998) , 10.1109/TEST.1998.743360
C. Thibeault, L. Boisvert, Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results international test conference. pp. 1019- 1026 ,(1998) , 10.1109/TEST.1998.743299
L. Rao, M.L. Bushnell, V.D. Agrawal, New graphical I/sub DDQ/ signatures reduce defect level and yield loss international conference on vlsi design. pp. 353- 360 ,(2003) , 10.1109/ICVD.2003.1183162
C. Thibeault, L. Boisvert, Can the current behavior of faulty and fault-free ICs and the impact on diagnosis defect and fault tolerance in vlsi and nanotechnology systems. pp. 202- 210 ,(1998) , 10.1109/DFTVS.1998.732167
K.M. Wallquist, Achieving I/sub DDQ/I/sub SSQ/ production testing with QuiC- IEEE Design & Test of Computers. ,vol. 12, pp. 62- 69 ,(1995) , 10.1109/MDT.1995.466382
W.R. Daasch, R. Madge, Variance reduction and outliers: statistical analysis of semiconductor test data international test conference. pp. 9- ,(2005) , 10.1109/TEST.2005.1583988
Anne Gattiker, Current Signatures for Production Testing IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96). pp. 25- ,(1996)