作者: TO-SING LI
关键词: Simulation 、 Rectangular potential barrier 、 Carrier scattering 、 Polycrystalline silicon 、 Oxide 、 Silicon 、 Grain boundary 、 Materials science 、 Transistor 、 Optoelectronics 、 Thin-film transistor
摘要: A two-dimensional non-planar device simulator for poly-Si TFT is developed, in which the influences of trapped charges and carrier scattering within grain boundary are incorporated into Poisson's equation drift-diffusion current formulations, respectively. With this simulator, I-V characteristics devices can be characterized. Thin-film transistors on polycrystalline silicon were fabricated testing. Excellent agreement between simulated results experimental data has been obtained. Some characteristics, such as ‘pseudo-subthreshold’ region, activation energy barrier height investigated elucidated by our simulator. Finally, making use we have effects film gate oxide thickness characteristics; predict that scaling down will drastically improve driving capability reducing potential barrier.