作者: P.-S. Lin , J.-Y. Guo , C.-Y. Wu
DOI: 10.1109/16.47771
关键词: Channel length modulation 、 Field-effect transistor 、 Rectangular potential barrier 、 Grain boundary 、 Materials science 、 Optoelectronics 、 Electronic engineering 、 Thin-film transistor 、 Transconductance 、 Polycrystalline silicon 、 Gate oxide
摘要: A physical model considering the effects of grain boundaries on turn-on behavior polysilicon thin-film transistors (poly-Si TFTs) is presented. Along channel, formation potential barrier near boundary proposed to account for low transconductance and high voltage TFTs. The height expressed in terms channel doping, gate oxide thickness, size, external as well drain biases. Drain bias results an asymmetric introduces more carrier injection from lowered side. It shown that this consideration very important characterizing saturation region under large drain-bias conditions. On basis developed model, I-V characteristics are described by interfacial-layer thermionic-diffusion model. Thin-film polycrystalline silicon with a coplanar structure were fabricated testing. Comparisons show excellent agreement between experimental data. >