A 10-b 20-Msample/s analog-to-digital converter
作者： S.H. Lewis , H.S. Fetterman , G.F. Gross , R. Ramachandran , T.R. Viswanathan
DOI: 10.1109/4.121557
关键词:
摘要: A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The uses pipelined nine-stage architecture with fully differential analog circuits and achieves signal-to-noise-and-distortion ratio (SNDR) of 60 dB full-scale sinusoidal input at 5 MHz. It occupies 8.7 mm/sup 2/ dissipates 240 mW. >
harvard.edu
core.ac.uk
sci-hub.se 参考文章(15)
A. Matsuzawa, M. Kagawa, M. Kanoh, K. Tatehara, T. Yamaoka, K. Shimizu, A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H international solid-state circuits conference. pp. 162- 163 ,(1990) , 10.1109/ISSCC.1990.110177
B. Zojer, B. Astegher, H. Jessner, R. Petschacher, A 10 b 75 MHz subranging A/D converter international solid-state circuits conference. pp. 164- 165 ,(1990) , 10.1109/ISSCC.1990.110178
G.C. Temes, High-accuracy pipeline A/D convertor configuration Electronics Letters. ,vol. 21, pp. 762- 763 ,(1985) , 10.1049/EL:19850537
D. Senderowicz, S.F. Dreyer, J.H. Huggins, C.F. Rahim, C.A. Laber, A family of differential NMOS analog circuits for a PCM codec filter chip IEEE Journal of Solid-state Circuits. ,vol. 17, pp. 1014- 1023 ,(1982) , 10.1109/JSSC.1982.1051855
S.H. Lewis, P.R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter IEEE Journal of Solid-State Circuits. ,vol. 22, pp. 954- 961 ,(1987) , 10.1109/JSSC.1987.1052843
Y.-M. Lin, B. Kim, P.R. Gray, A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS IEEE Journal of Solid-state Circuits. ,vol. 26, pp. 628- 636 ,(1991) , 10.1109/4.75065
B.-S. Song, S.-H. Lee, M.F. Tompsett, A 10-b 15-MHz CMOS recycling two-step A/D converter international solid-state circuits conference. ,vol. 25, pp. 1328- 1338 ,(1990) , 10.1109/4.62176
J.G. Peterson, A monolithic video A/D converter IEEE Journal of Solid-state Circuits. ,vol. 14, pp. 932- 937 ,(1979) , 10.1109/JSSC.1979.1051300
G. Nicollini, P. Confalonieri, D. Senderowicz, A fully differential sample-and-hold circuit for high-speed applications IEEE Journal of Solid-state Circuits. ,vol. 24, pp. 1461- 1465 ,(1989) , 10.1109/JSSC.1989.572640
S. Sutarja, P.R. Gray, A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter IEEE Journal of Solid-state Circuits. ,vol. 23, pp. 1316- 1323 ,(1988) , 10.1109/4.90027