A new twisted differential line structure in global bus design

Zhanyuan Jiang , Shiyan Hu , Weiping Shi
design automation conference 180 -183

2
2007
Improving boundary element methods for parasitic extraction

Shu Yan , Jianguo Liu , Weiping Shi
asia and south pacific design automation conference 261 -267

2
2003
Making fast buffer insertion even faster via approximation techniques

Zhuo Li , CN Sze , Charles J Alpert , Jiang Hu
asia and south pacific design automation conference 1 13 -18

28
2005
Macro Model of Advanced Devices for Parasitic Extraction

Yuhan Zhou , Yong Zhang , Vivek Sarin , Wangqi Qiu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35 ( 10) 1721 -1729

2
2016
Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Zhuo Li , David A Papa , Charles J Alpert , Shiyan Hu
international symposium on physical design 75 -82

4
2010
Fast characterization of parameterized cell library

Uday Doddannagari , Shiyan Hu , Weiping Shi
international symposium on quality electronic design 500 -505

1
2009
The impact of BEOL lithography effects on the SRAM cell performance and yield

Ying Zhou , Rouwaida Kanj , Kanak Agarwal , Zhuo Li
international symposium on quality electronic design 607 -612

7
2009
Probabilistic Congestion Prediction with Partial Blockages

Zhuo Li , Charles J Alpert , Stephen T Quay , Sachin Sapatnekar
international symposium on quality electronic design 841 -846

36
2007
An Efficient Algorithm for RLC Buffer Insertion

Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Weiping Shi
international symposium on quality electronic design 171 -175

1
2007
37
2006
Fast algorithms for slew constrained minimum cost buffering

Shiyan Hu , Charles J Alpert , Jiang Hu , Shrirang Karandikar
design automation conference 308 -313

18
2006
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Interconnects in Packages

Yang Yi , Peng Li , Vivek Sarin , Weiping Shi
electrical performance of electronic packaging 99 -102

2
2006
An efficient inductance extraction algorithm for 3-D interconnects with frequency dependent nonlinear magnetic materials

Yang Yi , Vivek Sarin , Weiping Shi
electrical performance of electronic packaging 217 -220

2008
A new RLC buffer insertion algorithm

Zhanyuan Jiang , Shiyan Hu , Jiang Hu , Zhuo Li
international conference on computer aided design 553 -557

4
2006
Circuit-wise buffer insertion and gate sizing algorithm with scalability

Zhanyuan Jiang , Weiping Shi
design automation conference 708 -713

5
2008
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes

Rouwaida Kanj , Rajiv Joshi , Zhou Li , JB Kuang
international symposium on low power electronics and design 87 -92

2
2008
Path based buffer insertion

Chin Ngai Sze , Charles J Alpert , Jiang Hu , Weiping Shi
design automation conference 509 -514

23
2005
Fast Electromagnetic Transient Simulation Based on Hierarchical Low-Rank Approximation

Lu Zhang , Bin Wang , Dongqi Wu , Le Xie
2019 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference (ISGT) 1 -5

1
2019
Buffering Interconnect for Multicore Processor Designs

Yifang Liu , Jiang Hu , Weiping Shi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 ( 12) 2183 -2196

3
2008
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics

Yang Yi , Peng Li , Vivek Sarin , Weiping Shi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 ( 11) 1918 -1927

13
2008